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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8522
LOW SKEW, 1-TO-17 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
FEATURES
* 17 LVHSTL outputs each with the ability to drive 50 to ground * Selectable differential CLK, nCLK or LVPECL clock inputs * CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL * PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL * Maximum output frequency: 500MHz * Translates any single-ended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels with resistor bias on nCLK input * Output skew: 50ps (typical) * Part-to-part skew: 70ps (typical) * VOH = 1.2V (maximum) * 3.3V core,1.8V output operating supply voltages * 0C to 70C ambient operating temperature
GENERAL DESCRIPTION
The ICS8522 is a low skew, 1-to-17 Differentialto-LVHSTL Fanout Buffer and a member of the HiPerClockSTM HiPerClockSTM Family of High Performance Clock Solutions from ICS. The ICS8522 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.
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Guaranteed output skew, part-to-part skew and crossover voltage characteristics make the ICS8522 ideal for interfacing to today's most advanced microprocessor and static RAMs.
BLOCK DIAGRAM
CLK_EN D Q LE CLK nCLK PCLK nPCLK 0 Q0:Q16 nQ0:nQ16
PIN ASSIGNMENT
VDDO nQ0 nQ1 nQ2 nQ3 nQ4 nQ5
VDDO nc VDD VDD CLK nCLK CLK_SEL PCLK nPCLK GND CLK_EN GND VDDO
1 2 3 4 5 6 7 8 9
52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
Q0
Q1
Q2
Q3
Q4
Q5
VDDO Q6 nQ6 Q7 nQ7 Q8 nQ8 VDDO Q9 nQ9 Q10 nQ10 VDDO
1
CLK_SEL
ICS8522
33 32 31 30 29 28
10 11 12
13 27 14 15 16 17 18 19 20 21 22 23 24 25 26
nQ16 Q16 nQ15 Q15 nQ14 Q14 VDDO nQ13 Q13 nQ12 Q12 nQ11 Q11
52-Lead LQFP 10mm x 10mm x 1.4mm body package Y package Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 8522CY www.icst.com/products/hiperclocks.html REV. A NOVEMBER 19, 2002
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8522
LOW SKEW, 1-TO-17 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
Type Description Output supply pins. No connect. Core supply pins. Pulldown Non-inver ting differential clock input. Inver ting differential clock input. Clock select input. When HIGH, selects CLK, nCLK inputs. Pulldown When LOW, selects PCLK, nPCLK inputs. LVCMOS / LVTTL interface levels. Pulldown Non-inver ting differential LVPECL clock input. Pullup Inver ting differential LVPECL clock input. Power supply ground. Synchronizing clock enable. When HIGH, clock outputs follows clock input. When LOW, Q outputs are forced low, nQ outputs are forced high. LVCMOS / LVTTL interface levels. Differential clock outputs. LVHSTL interface levels. Differential clock outputs. LVHSTL interface levels. Differential clock outputs. LVHSTL interface levels. Pullup
TABLE 1. PIN DESCRIPTIONS
Number 1, 13, 20, 27, 32, 39, 46 2 3, 4 5 6 7 8 9 10, 12 11 14, 15 16, 17 18, 19 Name VDDO nc VDD CLK nCLK CLK_SEL PCLK nPCLK GND CLK_EN nQ16, Q16 nQ15, Q15 nQ14, Q14 Power Unused Power Input Input Input Input Input Power Input Output Output Output
Pullup
21, 22 nQ13, Q13 Output Differential clock outputs. LVHSTL interface levels. 23, 24 nQ12, Q12 Output Differential clock outputs. LVHSTL interface levels. 25, 26 nQ11, Q11 Output Differential clock outputs. LVHSTL interface levels. 28, 29 nQ10, Q10 Output Differential clock outputs. LVHSTL interface levels. 30, 31 nQ9, Q9 Output Differential clock outputs. LVHSTL interface levels. 33, 34 nQ8, Q8 Output Differential clock outputs. LVHSTL interface levels. 35, 36 nQ7, Q7 Output Differential clock outputs. LVHSTL interface levels. 37, 38 nQ6, Q6 Output Differential clock outputs. LVHSTL interface levels. 40, 41 nQ5, Q5 Output Differential clock outputs. LVHSTL interface levels. 42, 43 nQ4, Q4 Output Differential clock outputs. LVHSTL interface levels. 44, 45 nQ3, Q3 Output Differential clock outputs. LVHSTL interface levels. 47, 48 nQ2, Q2 Output Differential clock outputs. LVHSTL interface levels. 49, 50 nQ1, Q1 Output Differential clock outputs. LVHSTL interface levels. 51, 52 nQ0, Q0 Output Differential clock outputs. LVHSTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. NOTE: Unused output pairs must be terminated.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor 51 51 Test Conditions Minimum Typical Maximum 4 Units pF K K
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REV. A NOVEMBER 19, 2002
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8522
LOW SKEW, 1-TO-17 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
Outputs Selected Source CLK, nCLK Q0:Q16 LOW CLK nQ0:nQ16 HIGH CLK
TABLE 3A. CONTROL INPUT FUNCTION TABLE
CLK_EN 0 1 Inputs CLK_SEL X 0
1 1 PCLK, nPCLK PCLK PCLK After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode the state of the outputs are a function of the CLK, nCLK and PCLK, nPCLK inputs as described in Table 3B.
Disabled
nCLK, nPCLK CLK, PCLK
Enabled
CLK_EN
nQ0 - nQ16 Q0 - Q16
FIGURE 1. CLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs CLK or PCLK nCLK or nPCLK 0 0 1 0 1 Biased; NOTE 1 Biased; NOTE 1 1 Biased; NOTE 1 Biased; NOTE 1 0 1 Outputs Q0:Q16 nQ0:nQ16 LOW HIGH HIGH LOW HIGH HIGH LOW LOW HIGH LOW LOW HIGH Input to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Inver ting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
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REV. A NOVEMBER 19, 2002
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8522
LOW SKEW, 1-TO-17 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 42.3C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V10%, TA=0C TO 70C
Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Ouptut Power Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 3.135 1.6 Typical 3.3 1.8 152 420 Maximum 3.465 2.0 200 Units V V mA mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V10%, TA=0C TO 70C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current CLK_EN CLK_SEL CLK_EN CLK_SEL -150 -5 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0.8 5 150 Units V V A A A A
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V10%, TA=0C TO 70C
Symbol Parameter IIH IIL VPP Input High Current Input Low Current CLK nCLK CLK nCLK Test Conditions VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 0.15 1.3 VDD - 0.85 Minimum Typical Maximum 150 5 Units A A A A V V
Peak-to-Peak Input Voltage
VCMR Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK and nCLK is VDD + 0.3V.
8522CY
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REV. A NOVEMBER 19, 2002
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8522
LOW SKEW, 1-TO-17 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
Test Conditions PCLK nPCLK PCLK nPCLK VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 0.3 1 VDD Minimum Typical Maximum 150 5 Units A A A A V V
TABLE 4D. LVPECL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V10%, TA=0C TO 70C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2 GND + 1.5 VCMR NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is VDD + 0.3V.
TABLE 4E. LVHSTL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V10%, TA=0C TO 70C
Symbol Parameter Test Conditions Output High Voltage VOH NOTE 1 Output Low Voltage; VOL NOTE 1 Output Crossover Voltage VOX Peak-to-Peak VSWING Output Voltage Swing NOTE 1: Outputs terminated with 50 to ground. Minimum 1.0 0 40% x (VOH-VOL) + VOL 0.6 0.73 Typical Maximum 1.2 0.4 60% x (VOH-VOL) + VOL 1.1 Units V V V V
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V10%, TA=0C TO 70C
Symbol fMAX tpLH tpHL Parameter Output Frequency Propagation Delay, Low-to-High; NOTE 1 Propagation Delay, High-to-Low; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise Time Output Fall Time 20% to 80% 20% to 80% f 500MHz f 500MHz 2.5 2.5 50 70 530 530 Test Conditions Minimum Typical Maximum 500 Units MHz ns ns ps ps ps ps %
tsk(o) tsk(pp)
tR tF
odc Output Duty Cycle 50 All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions at the same temperature. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8522CY
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REV. A NOVEMBER 19, 2002
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8522
LOW SKEW, 1-TO-17 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
1.8V 0.2V 3.3V 5%
VDD
V DD VDDO
Qx
SCOPE
nCLK, nPCLK
LVHSTL
nQx
V
CLK, PCLK
PP
Cross Points
V
CMR
GND GND = 0V
3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx nQ nQy Qy
PART 1 nQx Qx PART 2 nQy Qy
tsk(o)
tsk(pp)
OUTPUT SKEW
PART-TO-PART SKEW
nCLK, nPCLK CLK, PCLK nQ0:nQ16 Q0:Q16
tPD
80%
80% VO D
20% Clock Outputs t
R
20% t
F
PROPAGATION DELAY
nQ0:nQ16 Q0:Q16
OUTPUT RISE/FALL TIME
Pulse Width t
PERIOD
odc =
t PW t PERIOD
odc & tPERIOD
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REV. A NOVEMBER 19, 2002
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8522
LOW SKEW, 1-TO-17 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K CLK_IN + V_REF C1 0.1uF R2 1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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REV. A NOVEMBER 19, 2002
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8522
LOW SKEW, 1-TO-17 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8522. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS8522 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 200mA = 693mW Power (outputs)MAX = 32.8mW/Loaded Output pair If all outputs are loaded, the total power is 17 * 32.8mW = 557.6mW
Total Power_MAX (3.465V, with all outputs switching) = 693mW + 557.6mW = 1250.6mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 36.4C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 1.25W * 36.4C/W = 115.5C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE qJA
FOR
52-PIN LQFP, FORCED CONVECTION
qJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 58.0C/W 42.3C/W
200
47.1C/W 36.4C/W
500
42.0C/W 34.0C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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REV. A NOVEMBER 19, 2002
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8522
LOW SKEW, 1-TO-17 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVHSTL output driver circuit and termination are shown in Figure 3.
VDDO
Q1
VOUT RL 50
FIGURE 3. LVHSTL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load.
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
Pd_H = (V
OH_MIN
/R ) * (V
L DDO_MAX
-V
OH_MIN
) )
Pd_L = (V
OL_MAX
/R ) * (V
L DDO_MAX
-V
OL_MAX
Pd_H = (1V/50) * (2V - 1V) = 20mW Pd_L = (0.4V/50) * (2V - 0.4V) = 12.8mW Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW
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REV. A NOVEMBER 19, 2002
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8522
LOW SKEW, 1-TO-17 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 58.0C/W 42.3C/W
200
47.1C/W 36.4C/W
500
42.0C/W 34.0C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8522 is: 1986
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REV. A NOVEMBER 19, 2002
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8522
LOW SKEW, 1-TO-17 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
PACKAGE OUTLINE - Y SUFFIX
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A2 b c D D1 E E1 e L q ccc 0.45 0 --0.05 1.35 0.22 0.09 BCC MINIMUM NOMINAL 52 --1.40 0.32 -12.00 BASIC 10.00 BASIC 12.00 BASIC 10.00 BASIC 0.65 BASIC ---0.75 7 0.08 1.60 0.15 1.45 0.38 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
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REV. A NOVEMBER 19, 2002
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8522
LOW SKEW, 1-TO-17 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
Marking ICS8522CY ICS8522CY Package 52 lead LQFP 52 lead LQFP on Tape and Reel Count 160 per tray 500 Temperature 0C to 70C 0C to 70C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS8522CY ICS8522CYT
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8522CY
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REV. A NOVEMBER 19, 2002

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